Registers in LPC2148

3.3.1. IRQ Status Register, VICIRQSTATUS

The VICIRQSTATUS Register provides the status of interrupts [31:0] after IRQ masking. Because of the use of dual-stage synchronization logic, the VICIRQSTATUS Register takes two clock cycles to update. This register can be accessed with zero wait states.

Note

To access the sampled status of the interrupts, use the ISS bit in the VICITCR Register

Table 3.2. VICIRQSTATUS Register bit assignments

Bits	Name	Type	Function
[31:0]	IRQStatus	Read	Shows the status of the interrupts after masking by the VICINTENABLE and VICINTSELECT Registers: 0 = interrupt is inactive (reset) 1 = interrupt is active. There is one bit of the register for each interrupt source.

Note

When a system has multiple VICs, and the VICIRQSTATUS Register is used to determine which interrupt source must be served (instead of using the VIC port or reading the VICADDRESS Register), the interrupt handler might have to read the VICIRQSTATUS Register of all the VICs in the system. This is because the interrupt status from daisy-chained VICs cannot be observed from the VICIRQSTATUS Register for the first VIC connected to the processor.

3.3.2. FIQ Status Register, VICFIQSTATUS

The VICFIQSTATUS Register provides the status of the interrupts after FIQ masking. The VICFIQSTATUS Register is 32 bits wide. There is normally only one FIQ in the system. You can allow more than one interrupt source to generate a FIQ. The FIQ handler can then read this register to determine which FIQ interrupt source is active. Because of the use of dual-stage synchronization logic, the VICFIQSTATUS Register takes two clock cycles to update. This register can be accessed with zero wait states.

Table 3.3. VICFIQSTATUS Register bit assignments

Bits	Name	Type	Function
[31:0]	FIQStatus	Read	Shows the status of the FIQ interrupts after masking by the VICINTENABLE and VICINTSELECT Registers: 0 = interrupt is inactive (reset) 1 = interrupt is active. There is one bit of the register for each interrupt source.

Note

This register is 32 bits wide to allow the FIQ to be placed on any of the input interrupt lines, but a typical system only contains one FIQ interrupt source.

When a system has multiple VICs, and the FIQ source can be located on a daisy-chained VIC, the interrupt handler might have to read the VICFIQSTATUS Register of all the VICs in the system. This is because the interrupt status from daisy-chained VICs cannot be observed from the VICFIQSTATUS Register for the first VIC connected to the processor.

3.3.3. Raw Interrupt Status Register, VICRAWINTR

The VICRAWINTR Register provides the unmasked status of the interrupt sources (either hardware or software). Because of the use of dual-stage synchronization logic, the VICRAWINTR Register takes two clock cycles to update. This register can be accessed with zero wait states.

Table 3.4. VICRAWINTR Register bit assignments

Bits	Name	Type	Function
[31:0]	RawInterrupt	Read	Shows the status of the interrupts before masking by the Enable Registers: 0 = interrupt is inactive before masking 1 = interrupt is active before masking. Because this register provides a direct view of the raw interrupt inputs, the reset value is unknown. There is one bit of the register for each interrupt source.

3.3.4. Interrupt Select Register, VICINTSELECT

The VICINTSELECT Register selects whether the corresponding interrupt source generates an FIQ or IRQ interrupt. This register can be accessed with zero wait states.

Table 3.5. VICINTSELECT Register bit assignments

Bits	Name	Type	Function
[31:0]	IntSelect	Read/write	Selects type of interrupt for interrupt request: 0 = IRQ interrupt (reset) 1 = FIQ interrupt. There is one bit of the register for each interrupt source.

Note

A standard system only has one FIQ source, so only one bit of this register must be set HIGH. This register must only be modified when the relevant interrupts are disabled. Changing the type of an interrupt when it is currently active and enabled can result in unpredictable behavior.

3.3.5. Interrupt Enable Register, VICINTENABLE

The VICINTENABLE Register enables the interrupt request lines, by unmasking the interrupt sources for the IRQ interrupt. This register can be accessed with zero wait states.

Table 3.6. VICINTENABLE Register bit assignments

Bits	Name	Type	Function
[31:0]	IntEnable	Read/write	Enables the interrupt request lines, which allow the interrupts to reach the processor. Read: 0 = interrupt disabled (reset) 1 = interrupt enabled. The interrupt enable can only be set using this register. The VICINTENCLEAR Register must be used to disable the interrupt enable. Write: 0 = no effect 1 = interrupt enabled. On reset, all interrupts are disabled. There is one bit of the register for each interrupt source.

3.3.6. Interrupt Enable Clear Register, VICINTENCLEAR

The VICINTENCLEAR Register clears bits in the VICINTENABLE Register, and masks out the interrupt sources for the IRQ interrupt. This register can be accessed with zero wait states.

Table 3.7. VICINTENCLEAR Register bit assignments

Bits	Name	Type	Function
[31:0]	IntEnable Clear	Write	Clears corresponding bits in the VICINTENABLE Register: 0 = no effect 1 = interrupt disabled in VICINTENABLE Register. There is one bit of the register for each interrupt source.

3.3.7. Software Interrupt Register, VICSOFTINT

The VICSOFTINT Register is used to generate software interrupts. This register can be accessed with zero wait states.

Table 3.8. VICSOFTINT Register bit assignments

Bits	Name	Type	Function
[31:0]	SoftInt	Read/write	Setting a bit HIGH generates a software interrupt for the selected source before interrupt masking. Read: 0 = software interrupt inactive (reset) 1 = software interrupt active. Write: 0 = no effect 1 = software interrupt enabled. There is one bit of the register for each interrupt source.

3.3.8. Software Interrupt Clear Register, VICSOFTINTCLEAR

The VICSOFTINTCLEAR Register clears bits in the VICSOFTINT Register.This register can be accessed with zero wait states.

Table 3.9. VICSOFTINTCLEAR Register bit assignments

Bits	Name	Type	Function
[31:0]	SoftIntClear	Write	Clears corresponding bits in the VICSOFTINT Register: 0 = no effect 1 = software interrupt disabled in the VICSOFTINT Register. There is one bit of the register for each interrupt source.

3.3.9. Protection Enable Register, VICPROTECTION

The VICPROTECTION Register enables or disables protected register access, stopping register accesses when the processor is in User mode. This register can be accessed with zero wait states.

Table 3.10. VICPROTECTION Register bit assignments

Bits	Name	Type	Function
[31:1]	Reserved	-	Reserved, read as zero, do not modify.
[0]	Protection	Read/write	Enables or disables protected register access: 0 = protection mode disabled (reset) 1 = protection mode enabled. When enabled, only privileged mode accesses (reads and writes) can access the interrupt controller registers, that is, when HPROT[1] is set HIGH for the current transfer. When disabled, both user mode and privileged mode can access the registers. This register can only be accessed in privileged mode, even when protection mode is disabled.

3.3.10. Vector Address Register, VICADDRESS

The VICADDRESS Register contains the Interrupt Service Routine (ISR) address of the currently active interrupt. If no interrupt is currently active, the register holds the ISR address of the last active interrupt. This register can be accessed with zero wait states.

Table 3.11. VICADRESS Register bit assignments

Bits	Name	Type	Function
[31:0]	VectAddr	Read/write	Contains the address of the currently active ISR, with reset value 0x00000000. A read of this register returns the address of the ISR and sets the current interrupt as being serviced. A read must only be performed while there is an active interrupt. A write of any value to this register clears the current interrupt. A write must only be performed at the end of an interrupt service routine.

Note

Reading from this register provides the address of the ISR, and indicates to the priority hardware that the interrupt is being serviced. Writing to this register indicates to the priority hardware that the interrupt has been serviced. The register must be used as follows:

·         the ISR reads the VICADDRESS Register when an IRQ interrupt is generated

·         at the end of the ISR, the VICADDRESS Register is written to, to update the priority hardware.

Reading or writing to this register at other times can cause incorrect operation.

3.3.11. Software Priority Mask Register, VICSWPRIORITYMASK

The VICSWPRIORITYMASK Register contains the mask value for the interrupt priority levels. This register can be accessed with zero wait states.

Table 3.12. VICSWPRIORITYMASK Register bit assignments

Bits	Name	Type	Function
[31:16]	Reserved	-	Reserved, read as zero, do not modify.
[15:0]	SWPriorityMask	Read/write	Controls software masking of the 16 interrupt priority levels: 0 = interrupt priority level is masked 1 = interrupt priority level is not masked (reset). Each bit of the register is applied to each of the 16 interrupt priority levels.

3.3.12. Vector Address Registers, VICVECTADDR[0-31]

The VICVECTADDR[0-31] Registers contain the ISR vector addresses. These registers can be accessed with one wait state.

Table 3.13. VICVECTADDR[0-31] Register bit assignments

Bits	Name	Type	Function
[31:0]	VectorAddr 0-31	Read/write	Contains ISR vector addresses.

Note

These registers must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior.

If the system does not support interrupt vector addresses, the VICVECTADDR Registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined.

3.3.13. Vector Priority Registers, VICVECTPRIORITY[0-31] and VICVECTPRIORITYDAISY

The VICVECTPRIORITY[0-31] and VICVECTPRIORITYDAISY Registers select the interrupt priority level for the 32 vectored interrupt sources, and the daisy chain input. The value can be from 0-15. The default values have all interrupts on the same priority level, 15, which is the lowest. This enables any of the vectored interrupts to be promoted to a higher priority with one simple register write. These registers can be accessed with one wait state.

Table 3.14. VICVECTPRIORITY[0-31] and VICVECTPRIORITYDAISY Register bit assignments

Bits	Name	Type	Function
[31:4]	Reserved	-	Reserved, read as zero, do not modify.
[3:0]	VectPriority	Read/write	Selects vectored interrupt priority level. You can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0-15.

Note

Hardware priority levels only take effect when multiple interrupts are programmed to have the same priority level and occur at the same time. In this case, vectored interrupt 0 has the highest priority, and interrupt 31 has the lowest priority.

If the VIC is used as part of a daisy-chain configuration in VIC0 mode, ensure that the interrupt service routine does not change the VICVECTPRIORITYDAISY register to a higher priority.

3.3.14. Peripheral Identification Registers, VICPERIPHID0-3

The VICPERIPHID0-3 Registers are four 8-bit registers, that span address locations 0xFE0-0xFEC. The registers can conceptually be treated as a single 32-bit register. The read-only registers provide the following options of the peripheral:

Part number [11:0]

This identifies the peripheral. The three digit product code 0x192 is used for the PrimeCell VIC.

Designer [19:12]

This is the identification of the designer. ARM Limited is 0x41 (ASCII A).

Revision number [23:20]

This is the revision number of the peripheral. The revision number starts from 0 and the value is revision-dependent.

Configuration [31:24]

This is the configuration option of the peripheral. The configuration value is 0.

Figure 3.1. Peripheral Identification Register bit assignment

The four 8-bit peripheral identification registers are described in the following sections:

VICPERIPHID0 Register

The VICPERIPHID0 Register is hard-coded and the fields within the register determine the reset value.

Table 3.15. VICPERIPHID0 Register bit assignments

Bits	Name	Type	Function
[31:8]	-	-	Reserved, read as zero, do not modify.
[7:0]	Partnumber0	Read	These bits read back as 0x192.

VICPERIPHID1 Register

Table 3.16. VICPERIPHD1 Register bit assignments

Bits	Name	Type	Function
[31:8]	-	-	Reserved, read as zero, do not modify.
[7:4]	Designer0	Read	These bits read back as 0x1.
[3:0]	Partnumber1	Read	These bits read back as 0x1.

VICPERIPHID2 Register

Table 3.17. VICPERIPHID2 Register bit assignments

Bits	Name	Type	Function
[31:8]	-	-	Reserved, read as zero, do not modify.
[7:4]	Revision	Read	These bits read back as the revision number, which can be between 0 and 15.
[3:0]	Designer1	Read	These bits read back as 0x4.

VICPERIPHID3 Register

Table 3.18. VICPERIPHID3 Register bit assignments

Bits	Name	Type	Function
[31:8]	-	-	Reserved, read as zero, do not modify.
[7:2]	Configuration	Read	These bits read back as 0x0.
[1:0]	Configuration	Read	Indicates the number of interrupts supported: 00 = 32 (default) 01 = 64 10 = 128 11 = 256.

3.3.15. PrimeCell Identification Registers, VICPCELLID0-3

The VICPCELLID0-3 Registers are four 8-bit registers, that span address locations 0xFF0-0xFFC. The read-only register can conceptually be treated as a single 32-bit register. The register is used as a standard cross-peripheral identification system.

Figure 3.2. PrimeCell Identification Register bit assignment

The four 8-bit registers are described in the following subsections:

VICPCELLID0 Register

Table 3.19. VICPCELLID0 Register bit assignments

Bits	Name	Type	Function
[31:8]	-	-	Reserved, read as zero, do not modify.
[7:0]	VICPCellID0	Read	These bits read back as 0x0D.

VICPCELLID1 Register

Table 3.20. VICPCELLID1 Register bit assignments

Bits	Name	Type	Function
[31:8]	-	-	Reserved, read as zero, do not modify.
[7:0]	VICPCellID1	Read	These bits read back as 0xF0.

VICPCELLID2 Register

Table 3.21. VICPCELLID2 Register bit assignments

Bits	Name	Type	Function
[31:8]	-	-	Reserved, read as zero, do not modify.
[7:0]	VICPCellID2	Read	These bits read back as 0x05.

VICPCELLID3 Register

Table 3.22. VICPCELLID3 Register bit assignments

Bits	Name	Type	Function
[31:8]	-	-	Reserved, read as zero, do not modify.
[7:0]	VICPCellID3	Read	These bits read back as 0xB1.