ARM7 MCU Bus structure

ARM7 MCU Bus structure

ARM MCU has multiple bus structure. There are two types of Busses in ARM7 microcontroller – Advanced High performance BUS (AHB) and VPB bus. AHB is fast bus which is clocked directly by PLL and works at same speed as ARM core. So to AHB bus ARM core and Interrupt controller are directly connected while other peripherals are connected through VPB divider. VPB divider is capable to divide speed of AHB by 1; 2 and 4. so this means if VPB bus divider will be set to 4 and CPI core speed will be 60MHz, then MCU timer will run at speed 60/4=15MHz.

//C code snippet of VPB speed setting define divider:

#define PBSD 4

//define VPBDIV_VALUE needed to write to VPBDIV register

#define VPBDIV_VALUE (PBSD & 0x03)

//Write VPBDIV_VALUE to VPBDIV register to divide VHB frequency by PBSD:

VPBDIV = VPBDIV_VALUE;

When talking of buses wee need to mention, that there is one more bus connected to AHB via MAM (Memory Accelerator Module). MAM is used to accelerate Flash memory as it is capable to run at maximum speed of 20MHz while CPU core can run at like 80MHz. MAM is using some sort of cashing technique to achieve flach memory speed equal to cores peed.

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Compressed Thumb instructions of ARM MCU

Submitted by admin on Thu, 01/04/2007 - 19:04

Thumb instructions

Thumb instructions shrinks ARM instructions from 32 bit to 16 bit length. This allows saving up to 40% of program memory comparing to ARM instruction set. Maybe this is main reason of Thumb instructions being used. Thumb instructions loose many properties of ARM instructions and become similar to traditional RISC instructions. Thumb instructions cant be conditional, data processing have a two-address format where destination register is one of source registers.

ARM instruction: ADD R0, R0, R1

Thumb instruction: ADD R0, R1

As Thumb instruction set takes less of program space it allows to upload bigger applications but with lower speed as using ARM instructions performance is up to 40% faster. But in non critical applications or functions speed isn't significant factor.

Also Thumb instructions doesn't have full access to all registers. Thumb instructions can only access “low registers”(R0-R7). And only few instructions can access “high registers”(R8-R12).

Thumb decoding

Thumb instructions has to be decoded-decompressed to equivalent ARM instructions while executed. This is handled in instruction pipeline. Pipeline has additional de-compressor logic in series to instruction decoder, which firstly decompress Thumb instruction and then decode. This usually results in decode latency.

Changing to Thumb mode

Changing to Thumb mode is done by setting T-flag in CPSR register. This is usually done by executing BX(Branche exchange) instruction to address where the Thumb code begins. So same memory space may contain ARM-code and Thumb-code.

Some interesting facts about using Thumb:

• The Thumb code requires 70% of the space of the ARM code.
• The Thumb code uses 40% more instructions than the ARM code.
• With 32-bit memory, the ARM code is 40% faster than the Thumb code.
• With 16-bit memory, the Thumb code is 45% faster than the ARM code.
• Thumb code uses 30% less external memory power than ARM code.

This means that where performance is needed a system should use ARM instruction set, where cost and power consumption is important use Thumb instructions. Sometimes is better to use combination of both instruction sets. Where high end ARM system uses Thumb code in non critical routines to save power and memory space.

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ARM7 core instruction set explained

Submitted by admin on Thu, 01/04/2007 - 17:32

ARM7 architecture has normal 32bit ARM7 instruction set and compressed 16 bit instruction set so called “Thumb”. ARM7 instructions has a complex behaviour. As ARM processor programming is usually written in C there is no need to be ARM expert, but understanding of basics may help in developing efficient programs.

ARM7 datatypes

ARM7 processor can support following datatypes:

• 8 bit signed and unsigned bytes;
• 16 bit signed and unsigned half-words;
• 32 bit signed and unsigned words

But shorter then 32 bit datatypes are supported only by data transfer functions but when internally processed they are extended to 32 bit size. ARM7 core doesn't support floating point datatypes – they can only be interpreted by software.

ARM memory organisation

ARM7 is capable to store words in two ways depending on weather significant byte is stored. If word MSB is stored at highest byte then operation is called “little-endian” if MSB is stored at lowest position, then it is called “big-endian”.

Usually it is easier to work with little-endian for people as they expect to be LSB at lowest position. Endian is selected in compiler settings.

ARM conditional instructions

Comparing to other RISC microcontrollers almost all ARM7 core instructions are conditionally executed. As conditional branches are standard instructions ARM instructions were extended by adding 4 bit in the top of 32 bit instruction field:

As condition field has 4 bits, there can be 16 condition values. According to condition – instruction can be executed or skipped. As we know conditions depends on N, Z, C and V flags in CPSR register. Available conditions:

Don't use 'NV' as it will act as 'nop' operation. But it is reserved and may change in other ARM platforms. Behaviour of this is not guaranteed.

Conditional instructions are is one factor that keeps smooth program flow through pipeline. As we know when usual branch occur the pipeline is flushed and start refiling from beginning.

Practically speaking

if(x<100)

{

x++;

}

would compile in most efficient ASM code using one conditional command.

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ARM7 instruction groups

ARM7 instructions split in six main categories:

• Branching;
• Data processing;
• Data transfer;
• Block transfer;
• Multiply;
• Software interrupt.

Branching allows jumping forwards and backwards up to 32MB.

There are two main types of branching:

• Branch jump with/without link exchange (link exchange means that current PC value is stored ir R14 link register);
• Branching with/without link exchange and with instruction set exchange between ARM<->Thumb(The only recommended instruction to swap between ARM and Thumb).

Data processing includes all Logical, adding/subtracting, testing instructions (conditional/unconditional) like AND, EOR, SUB, RSB, ADD, ADC, SBC, RSC, TST, TEQ, CMP, CMN, ORR, MOV< BIC, MVN.

For instance compiler C code: if(z==1) R1=R2+(R3x4) should compile optimally to like

EQADDS R1, R2, R3, LSL #2

Data transfer instructions are used to move signed/unsigned Word, half-Word and Byte data to and from selected register. LDR and STR mnemonics.

Block transfer instructions are used to copy multiple registers with single instruction. Using LDM and STM instructions it is possible Load and Store whole register bank or subset.

Multiply instructions used for multiply operations. There are two subsets of operands MUL, MLA for 32bit results and MULL, MLAL for 64 bit results.

Software interrupt instruction SWI transfers execution to address in memory location 0x00000008 and changes mode to svc. SWI instruction can also be conditional. SWI instruction has 24 unused bits that can be used for storing data or or custom code which can be decoded in svc mode. This feature is handy in embedded OS when making operating system calls.

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ARM7 exception modes

Submitted by admin on Thu, 12/07/2006 - 13:02

This is an important part of understanding ARM operation modes and handling them. ARM7 supports seven types (0x00000014 address is reserved) of exceptions:

As you can see in the table each exception has its own name and fixed address so called exception vectors. When exception occurs, execution is forced from fixed memory address corresponding to the type of exception. When exception occurs R14 and SPSR registers acts like this:

R14_<mode>=return link(PC+4);

SPSR_<mode>=CPSR;

CPSR[4:0]=exception mode number;

//execute in ARM state

CPSR[5]=0;

//disable fast interrupts

if (<mode>==reset or FIQ) CPSR[6]=1;

//disable normal interrupts

CPSR[7]=1

PC=mode vector address

Each exception has priorities. Table bellow shows how priorities are assigned to exceptions:

Note. All chip peripherals are served as FIQ and IRQ.

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ARM7 MCU registers

Submitted by admin on Thu, 12/07/2006 - 11:46

ARM has 31 general purpose 32 bit register where 16 of these are visible at any time. Other registers are used to speed up processing of exceptions. There also is 6 32bit wide status registers. Lets see how it looks like. Registers are arranged in partially overlapping banks with a different register ban of each MCU mode. As I mentioned at any time 15 general purpose registers(R0 to R14) and one or two status registers and PC are visible.

Basically R0-R12 registers are user register, that doesn't have special purpose. Registers R13 – R15 has special functions. R13 is used as stack pointer (SP), R14 is used as link register (LR) and R15 is as program counter (PC):

Additionally there is a Program status register CPSR which contains a number of flags of program status and control information. All modes have saved program status register SPSR of CPSR register except User/system mode.

• The N bit is the "negative flag" and indicates that a value is negative.
• The Z bit is the "zero flag" and is set when an appropriate instruction produces a zero result.
• The C bit is the "carry flag" but it can also be used to indicate "borrows" (from subtraction operations) and "extends" (from shift instructions (LINK)).
• The V bit is the "overflow flag" which is set if an instruction produces a result that overflows and hence may go beyond the range of numbers that can be represented in 2's complement signed format.
• The I and F bits which determine whether interrupts (such as requests for input/output) are enabled or disabled.
• The T bit which indicates whether the processor is in "Thumb" mode, where the processor can execute a subset of the assembly language as 16-bit compact instructions. As Thumb code packs more instructions into the same amount of memory, it is an effective solution to applications where physical memory is at a premium.
• The M4 to M0 bits are the mode bits. Application programs normally run in user mode (where the mode bits are 10000). Whenever an interrupt or similar event occurs, the processor switches into one of the alternative modes allowing the software handler greater privileges with regard to memory manipulation.

ARM7 MCU has six operation modes and each mode has its own register configuration. For instance FIQ interrupt mode has duplicated R7 – R12 registers, program doesn't have to preserve registers in to stack. And of course R13 – R15 registers are duplicated in each following mode. Other registers (R0 to R7) are un-banked what means they are physically same and accessible in all modes.

ARM7 is a load-and-store architecture, where before processing any instruction the data has to be moved from memory to set of registers after execution data is stored back into memory.

Registers in LPC2148

3.3.1. IRQ Status Register, VICIRQSTATUS

The VICIRQSTATUS Register provides the status of interrupts [31:0] after IRQ masking. Because of the use of dual-stage synchronization logic, the VICIRQSTATUS Register takes two clock cycles to update. This register can be accessed with zero wait states.

Note

To access the sampled status of the interrupts, use the ISS bit in the VICITCR Register

Table 3.2. VICIRQSTATUS Register bit assignments

Bits	Name	Type	Function
[31:0]	IRQStatus	Read	Shows the status of the interrupts after masking by the VICINTENABLE and VICINTSELECT Registers: 0 = interrupt is inactive (reset) 1 = interrupt is active. There is one bit of the register for each interrupt source.

Note

When a system has multiple VICs, and the VICIRQSTATUS Register is used to determine which interrupt source must be served (instead of using the VIC port or reading the VICADDRESS Register), the interrupt handler might have to read the VICIRQSTATUS Register of all the VICs in the system. This is because the interrupt status from daisy-chained VICs cannot be observed from the VICIRQSTATUS Register for the first VIC connected to the processor.

3.3.2. FIQ Status Register, VICFIQSTATUS

The VICFIQSTATUS Register provides the status of the interrupts after FIQ masking. The VICFIQSTATUS Register is 32 bits wide. There is normally only one FIQ in the system. You can allow more than one interrupt source to generate a FIQ. The FIQ handler can then read this register to determine which FIQ interrupt source is active. Because of the use of dual-stage synchronization logic, the VICFIQSTATUS Register takes two clock cycles to update. This register can be accessed with zero wait states.

Table 3.3. VICFIQSTATUS Register bit assignments

Bits	Name	Type	Function
[31:0]	FIQStatus	Read	Shows the status of the FIQ interrupts after masking by the VICINTENABLE and VICINTSELECT Registers: 0 = interrupt is inactive (reset) 1 = interrupt is active. There is one bit of the register for each interrupt source.

Note

This register is 32 bits wide to allow the FIQ to be placed on any of the input interrupt lines, but a typical system only contains one FIQ interrupt source.

When a system has multiple VICs, and the FIQ source can be located on a daisy-chained VIC, the interrupt handler might have to read the VICFIQSTATUS Register of all the VICs in the system. This is because the interrupt status from daisy-chained VICs cannot be observed from the VICFIQSTATUS Register for the first VIC connected to the processor.

3.3.3. Raw Interrupt Status Register, VICRAWINTR

The VICRAWINTR Register provides the unmasked status of the interrupt sources (either hardware or software). Because of the use of dual-stage synchronization logic, the VICRAWINTR Register takes two clock cycles to update. This register can be accessed with zero wait states.

Table 3.4. VICRAWINTR Register bit assignments

Bits	Name	Type	Function
[31:0]	RawInterrupt	Read	Shows the status of the interrupts before masking by the Enable Registers: 0 = interrupt is inactive before masking 1 = interrupt is active before masking. Because this register provides a direct view of the raw interrupt inputs, the reset value is unknown. There is one bit of the register for each interrupt source.

3.3.4. Interrupt Select Register, VICINTSELECT

The VICINTSELECT Register selects whether the corresponding interrupt source generates an FIQ or IRQ interrupt. This register can be accessed with zero wait states.

Table 3.5. VICINTSELECT Register bit assignments

Bits	Name	Type	Function
[31:0]	IntSelect	Read/write	Selects type of interrupt for interrupt request: 0 = IRQ interrupt (reset) 1 = FIQ interrupt. There is one bit of the register for each interrupt source.

Note

A standard system only has one FIQ source, so only one bit of this register must be set HIGH. This register must only be modified when the relevant interrupts are disabled. Changing the type of an interrupt when it is currently active and enabled can result in unpredictable behavior.

3.3.5. Interrupt Enable Register, VICINTENABLE

The VICINTENABLE Register enables the interrupt request lines, by unmasking the interrupt sources for the IRQ interrupt. This register can be accessed with zero wait states.

Table 3.6. VICINTENABLE Register bit assignments

Bits	Name	Type	Function
[31:0]	IntEnable	Read/write	Enables the interrupt request lines, which allow the interrupts to reach the processor. Read: 0 = interrupt disabled (reset) 1 = interrupt enabled. The interrupt enable can only be set using this register. The VICINTENCLEAR Register must be used to disable the interrupt enable. Write: 0 = no effect 1 = interrupt enabled. On reset, all interrupts are disabled. There is one bit of the register for each interrupt source.

3.3.6. Interrupt Enable Clear Register, VICINTENCLEAR

The VICINTENCLEAR Register clears bits in the VICINTENABLE Register, and masks out the interrupt sources for the IRQ interrupt. This register can be accessed with zero wait states.

Table 3.7. VICINTENCLEAR Register bit assignments

Bits	Name	Type	Function
[31:0]	IntEnable Clear	Write	Clears corresponding bits in the VICINTENABLE Register: 0 = no effect 1 = interrupt disabled in VICINTENABLE Register. There is one bit of the register for each interrupt source.

3.3.7. Software Interrupt Register, VICSOFTINT

The VICSOFTINT Register is used to generate software interrupts. This register can be accessed with zero wait states.

Table 3.8. VICSOFTINT Register bit assignments

Bits	Name	Type	Function
[31:0]	SoftInt	Read/write	Setting a bit HIGH generates a software interrupt for the selected source before interrupt masking. Read: 0 = software interrupt inactive (reset) 1 = software interrupt active. Write: 0 = no effect 1 = software interrupt enabled. There is one bit of the register for each interrupt source.

3.3.8. Software Interrupt Clear Register, VICSOFTINTCLEAR

The VICSOFTINTCLEAR Register clears bits in the VICSOFTINT Register.This register can be accessed with zero wait states.

Table 3.9. VICSOFTINTCLEAR Register bit assignments

Bits	Name	Type	Function
[31:0]	SoftIntClear	Write	Clears corresponding bits in the VICSOFTINT Register: 0 = no effect 1 = software interrupt disabled in the VICSOFTINT Register. There is one bit of the register for each interrupt source.

3.3.9. Protection Enable Register, VICPROTECTION

The VICPROTECTION Register enables or disables protected register access, stopping register accesses when the processor is in User mode. This register can be accessed with zero wait states.

Table 3.10. VICPROTECTION Register bit assignments

Bits	Name	Type	Function
[31:1]	Reserved	-	Reserved, read as zero, do not modify.
[0]	Protection	Read/write	Enables or disables protected register access: 0 = protection mode disabled (reset) 1 = protection mode enabled. When enabled, only privileged mode accesses (reads and writes) can access the interrupt controller registers, that is, when HPROT[1] is set HIGH for the current transfer. When disabled, both user mode and privileged mode can access the registers. This register can only be accessed in privileged mode, even when protection mode is disabled.

3.3.10. Vector Address Register, VICADDRESS

The VICADDRESS Register contains the Interrupt Service Routine (ISR) address of the currently active interrupt. If no interrupt is currently active, the register holds the ISR address of the last active interrupt. This register can be accessed with zero wait states.

Table 3.11. VICADRESS Register bit assignments

Bits	Name	Type	Function
[31:0]	VectAddr	Read/write	Contains the address of the currently active ISR, with reset value 0x00000000. A read of this register returns the address of the ISR and sets the current interrupt as being serviced. A read must only be performed while there is an active interrupt. A write of any value to this register clears the current interrupt. A write must only be performed at the end of an interrupt service routine.

Note

Reading from this register provides the address of the ISR, and indicates to the priority hardware that the interrupt is being serviced. Writing to this register indicates to the priority hardware that the interrupt has been serviced. The register must be used as follows:

·         the ISR reads the VICADDRESS Register when an IRQ interrupt is generated

·         at the end of the ISR, the VICADDRESS Register is written to, to update the priority hardware.

Reading or writing to this register at other times can cause incorrect operation.

3.3.11. Software Priority Mask Register, VICSWPRIORITYMASK

The VICSWPRIORITYMASK Register contains the mask value for the interrupt priority levels. This register can be accessed with zero wait states.

Table 3.12. VICSWPRIORITYMASK Register bit assignments

Bits	Name	Type	Function
[31:16]	Reserved	-	Reserved, read as zero, do not modify.
[15:0]	SWPriorityMask	Read/write	Controls software masking of the 16 interrupt priority levels: 0 = interrupt priority level is masked 1 = interrupt priority level is not masked (reset). Each bit of the register is applied to each of the 16 interrupt priority levels.

3.3.12. Vector Address Registers, VICVECTADDR[0-31]

The VICVECTADDR[0-31] Registers contain the ISR vector addresses. These registers can be accessed with one wait state.

Table 3.13. VICVECTADDR[0-31] Register bit assignments

Bits	Name	Type	Function
[31:0]	VectorAddr 0-31	Read/write	Contains ISR vector addresses.

Note

These registers must only be updated when the relevant interrupts are disabled. Receiving an interrupt while the vector address is being written to can result in unpredictable behavior.

If the system does not support interrupt vector addresses, the VICVECTADDR Registers can be programmed with the numbers of the interrupt source ports they relate to, so that the source of the active interrupt can be easily determined.

3.3.13. Vector Priority Registers, VICVECTPRIORITY[0-31] and VICVECTPRIORITYDAISY

The VICVECTPRIORITY[0-31] and VICVECTPRIORITYDAISY Registers select the interrupt priority level for the 32 vectored interrupt sources, and the daisy chain input. The value can be from 0-15. The default values have all interrupts on the same priority level, 15, which is the lowest. This enables any of the vectored interrupts to be promoted to a higher priority with one simple register write. These registers can be accessed with one wait state.

Table 3.14. VICVECTPRIORITY[0-31] and VICVECTPRIORITYDAISY Register bit assignments

Bits	Name	Type	Function
[31:4]	Reserved	-	Reserved, read as zero, do not modify.
[3:0]	VectPriority	Read/write	Selects vectored interrupt priority level. You can select any of the 16 vectored interrupt priority levels by programming the register with the hexadecimal value of the priority level required, from 0-15.

Note

Hardware priority levels only take effect when multiple interrupts are programmed to have the same priority level and occur at the same time. In this case, vectored interrupt 0 has the highest priority, and interrupt 31 has the lowest priority.

If the VIC is used as part of a daisy-chain configuration in VIC0 mode, ensure that the interrupt service routine does not change the VICVECTPRIORITYDAISY register to a higher priority.

3.3.14. Peripheral Identification Registers, VICPERIPHID0-3

The VICPERIPHID0-3 Registers are four 8-bit registers, that span address locations 0xFE0-0xFEC. The registers can conceptually be treated as a single 32-bit register. The read-only registers provide the following options of the peripheral:

Part number [11:0]

This identifies the peripheral. The three digit product code 0x192 is used for the PrimeCell VIC.

Designer [19:12]

This is the identification of the designer. ARM Limited is 0x41 (ASCII A).

Revision number [23:20]

This is the revision number of the peripheral. The revision number starts from 0 and the value is revision-dependent.

Configuration [31:24]

This is the configuration option of the peripheral. The configuration value is 0.

Figure 3.1. Peripheral Identification Register bit assignment

The four 8-bit peripheral identification registers are described in the following sections:

VICPERIPHID0 Register

The VICPERIPHID0 Register is hard-coded and the fields within the register determine the reset value.

Table 3.15. VICPERIPHID0 Register bit assignments

Bits	Name	Type	Function
[31:8]	-	-	Reserved, read as zero, do not modify.
[7:0]	Partnumber0	Read	These bits read back as 0x192.

VICPERIPHID1 Register

Table 3.16. VICPERIPHD1 Register bit assignments

Bits	Name	Type	Function
[31:8]	-	-	Reserved, read as zero, do not modify.
[7:4]	Designer0	Read	These bits read back as 0x1.
[3:0]	Partnumber1	Read	These bits read back as 0x1.

VICPERIPHID2 Register

Table 3.17. VICPERIPHID2 Register bit assignments

Bits	Name	Type	Function
[31:8]	-	-	Reserved, read as zero, do not modify.
[7:4]	Revision	Read	These bits read back as the revision number, which can be between 0 and 15.
[3:0]	Designer1	Read	These bits read back as 0x4.

VICPERIPHID3 Register

Table 3.18. VICPERIPHID3 Register bit assignments

Bits	Name	Type	Function
[31:8]	-	-	Reserved, read as zero, do not modify.
[7:2]	Configuration	Read	These bits read back as 0x0.
[1:0]	Configuration	Read	Indicates the number of interrupts supported: 00 = 32 (default) 01 = 64 10 = 128 11 = 256.

3.3.15. PrimeCell Identification Registers, VICPCELLID0-3

The VICPCELLID0-3 Registers are four 8-bit registers, that span address locations 0xFF0-0xFFC. The read-only register can conceptually be treated as a single 32-bit register. The register is used as a standard cross-peripheral identification system.

Figure 3.2. PrimeCell Identification Register bit assignment

The four 8-bit registers are described in the following subsections:

VICPCELLID0 Register

Table 3.19. VICPCELLID0 Register bit assignments

Bits	Name	Type	Function
[31:8]	-	-	Reserved, read as zero, do not modify.
[7:0]	VICPCellID0	Read	These bits read back as 0x0D.

VICPCELLID1 Register

Table 3.20. VICPCELLID1 Register bit assignments

Bits	Name	Type	Function
[31:8]	-	-	Reserved, read as zero, do not modify.
[7:0]	VICPCellID1	Read	These bits read back as 0xF0.

VICPCELLID2 Register

Table 3.21. VICPCELLID2 Register bit assignments

Bits	Name	Type	Function
[31:8]	-	-	Reserved, read as zero, do not modify.
[7:0]	VICPCellID2	Read	These bits read back as 0x05.

VICPCELLID3 Register

Table 3.22. VICPCELLID3 Register bit assignments

Bits	Name	Type	Function
[31:8]	-	-	Reserved, read as zero, do not modify.
[7:0]	VICPCellID3	Read	These bits read back as 0xB1.